The present invention relates to an instruction buffer and a buffer queue control method and more particularly to an instruction buffer and a buffer queue control method capable of executing a plurality of instructions at high speed.
Pipeline processing is an implementation for the high-speed execution of a plurality of instructions. Pipeline processing divides the execution of instructions such that a group of instructions can exist at a plurality of different stages at any time. For example, pipeline processing includes a stage for fetching an instruction, a stage for decoding an instruction, a stage for issuing an instruction, and a stage for executing an instruction. An instruction may exist at the instruction issuing stage when another instruction exists at the instruction decoding stage.
Generally, a plurality of instructions are issued by either one of in-order issuance and out-of-order issuance. The in-order issuance sequentially issues instructions in the same order as a program. On the other hand, the out-of-order issuance first executes any instruction ready to be issued without regard to the order of a program.
The out-of-order issuance promotes the efficient issuance of instructions and thereby enhances the efficient use of, e.g., an arithmetic and logic unit (ALU), i.e., high-speed processing. However, the problem with the out-of-order issuance not dependent on a program is that instructions registered earlier than the others are apt to be left unexecuted, preventing instructions dependent on the above instructions from being issued. As a result, an instruction buffer is filled up with instructions, slowing down the entire processing.
Technologies relating to the present invention are disclosed in, e.g., Japanese patent laid-open publication Nos. 63-284673, 9-231203 and 11-272466, Japanese patent application published No. 8-504977, and Japanese Patent 2,503,984.